The present invention relates to a method for evaluating an SRAM (Static Random Access Memory) memory cell and a computer readable recording medium which records an evaluation program of the SRAM memory cell.
A semiconductor device which is constituted by forming a transistor on a semiconductor substrate is manufactured by using various microprocessing techniques which are developed to satisfy a demand for miniaturization and high integration, and the miniaturization and high packaging of the semiconductor device have been steadily advancing.
With respect to a semiconductor element such as a transistor which is manufactured using such microprocessing techniques, along with the miniaturization of the semiconductor element, it is not sufficient to simply decrease a size of the semiconductor element while maintaining a similar shape and a new design of semiconductor element becomes necessary. Particularly, as shown in FIG. 15, in an SRAM memory cell which is constituted of a flip-flop circuit having a first inverter 110 and a second inverter 120, it is necessary to adjust the specification of design on each transistor so as to impart a desired writing characteristic and a desired reading characteristic to the SRAM memory cell.
As a method for evaluating the characteristic of the SRAM memory cell, the evaluation of a static noise margin is used (see patent document 1, for example).
The static noise margin is an index which defines how the evaluation of the characteristic of the SRAM memory cell should be made, and the evaluation is made as follows.
An input/output characteristic of the first inverter 110 and an input/output characteristic of the second inverter 120 are obtained by applying a rated power source voltage VDD to word line W and bit lines BL, BL in the SRAM memory cell shown in FIG. 15 respectively. FIG. 16 shows the first inverter by extracting the first inverter from the SRAM memory cell shown in FIG. 15. Here, an output voltage outputted from a node Vs1 when an input voltage ranging from 0V to the rated power source voltage VDD is applied to a node Vs2 is obtained, and is used as the first input/output characteristic data. FIG. 17 shows an example of the first input/output characteristic data 130.
In the same manner, an output voltage outputted from a node Vs2 when an input voltage ranging from 0V to the rated power source voltage VDD is applied to a node Vs1 in the second inverter 120 shown in FIG. 18 is obtained, and is used as the second input/output characteristic data. Next, an X-Y axis conversion is performed by aligning the second input/output characteristic data with an axis of ordinate and an axis of abscissas of the first input/output characteristic data 130 thus newly forming the second input/output characteristic data. FIG. 19 shows an example of the second input/output characteristic data 140 obtained after the X-Y axis conversion.
By overlapping the first input/output characteristic data 130 and the second input/output characteristic data 140 obtained in this manner with each other, as shown in FIG. 20, two regions which are surrounded by a curve of the first input/output characteristic data 130 and a curve of the second input/output characteristic data 140 are formed. Maximum squares which inscribe these regions are respectively drawn, and a length of one side of the smaller square is defined as a static noise margin (SNM).
In the SRAM memory cell, the presence of these two squares is a prerequisite for holding information. The larger the square, that is, the larger a value of the static noise margin, the more stable information the memory cell can hold.    Patent document 1: JP-A-2005-310242
A recent microminiaturized SRAM memory cell is liable to be influenced by various irregularities at the time of the manufacture of the SRAM memory cell along with such microminiaturization thus giving rise to a drawback that characteristics of two inverters which constitute a flip-flop of the SRAM memory cell do not match each other.
The mismatch of characteristic of the inverters lowers the static noise margin value of the SRAM memory cell thus making a normal operation of the SRAM memory cell difficult.
Accordingly, in designing the SRAM memory cell, it is desirable to design the SRAM memory cell by taking various irregularities which may occur at the time of the manufacture of the SRAM memory cell into consideration and, for efficiently performing the evaluation of the various irregularities, there has been a demand for the efficient calculation of the static noise margin.
However, to define the static noise margin, as described previously, it is necessary to specify the maximum square which inscribes the region surrounded by the curve of the first input/output characteristic data and the curve of the second input/output characteristic data and hence, the square is specified by a manual operation. Accordingly, a huge amount of time is necessary for obtaining the static noise margin and hence, it is impossible to design the SRAM memory cell by taking all irregularities in the manufacture of the SRAM memory cell into consideration.
Under such circumstances, inventors of the present invention have made extensive studies for realizing the designing of an SRAM memory cell which enables the evaluation of a static noise margin in a shorter time and is hardly influenced by various irregularities which may occur at the time of the manufacture of the SRAM memory cell, and have completed the present invention.